| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| butt_key5 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| butt_key4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| butt_key3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| butt_key2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| butt_key1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| butt_key0 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key5 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key4 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key3 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| button_key0 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_rezult_serial0 |
14 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Code_ADC_Temper_conv0 |
14 |
8 |
0 |
8 |
40 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| LCD_12864_1 |
514 |
356 |
0 |
356 |
15 |
356 |
356 |
356 |
0 |
0 |
0 |
0 |
0 |
| ALT_PLL_1|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ALT_PLL_1 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1 |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal|u_control_fsm |
26 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0|control_internal |
13 |
1 |
0 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1|modular_adc_0 |
12 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC_Core_Core_1 |
12 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |